On chip embedded memory with non-volatility can enable energy and computational efficiency. However, leading embedded memory options such as STT-MRAM (Spin-Transfer Torque Magnetic Random Access Memory) suffer from high voltage and high current-density problems during the programming (i.e., writing) of a bit-cell.
FIG. 1 illustrates a two terminal 1T-1MTJ (Magnetic Tunnel Junction) bit-cell 100 for STT-MRAM. The read and write current paths for bit-cell 100 are identical, resulting in many design trade-offs. For example, during read operation, higher resistance of MTJ device is desired than during write operation. However, same current paths for passing read and write currents discourages from having different resistances for read and write operations. To write a logical high to bit-cell 100, Bit Line is raised relative to Source (or Select) Line, and to write a logical low to bit-cell 100, Bit Line is lowered relative to the Source Line. To read from bit-cell 100, Source Line is set to logical low and MTJ resistance is sensed using weak current (e.g., ⅛th of write current).
The 1T-1MTJ bit-cell 100 may have large write current (e.g., greater than 100 μA) and large voltage (e.g., greater than 0.7 V) requirements of tunnel junction based MTJ. The 1T-1MTJ bit-cell 100 may have high write error rates or low speed switching (e.g., exceeding 20 ns) in MTJ based MRAM. The 1T-1MTJ bit-cell 100 may also have reliability issues due to tunneling current in magnetic tunnel junctions. For example, insulator layer in the MTJ device is a barrier (e.g., 1KΩ to 10KΩ) which resists flow of large current, and lower current flow causes higher write errors.